The present invention relates to semiconductor memory devices, and more particularly to sensing schemes for such devices.
Memory devices are known in the art for storing data in a wide variety of electronic devices and applications. A typical memory device comprises a number of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line and a column of memory cells corresponds to a bit line, and where each memory cell defines a binary bit, i.e., either a zero (“0”) bit or a one (“1”) bit.
Typically, the state of a memory cell is determined during a read operation by sensing the current drawn by the memory cell. According to one particular embodiment, the current drawn by a particular memory cell is ascertained by connecting the drain terminal of the memory cell to a sensing circuit, where the source terminal of the memory cell is connected to ground, and the gate of the memory cell is selected. The sensing circuit attempts to detect the current drawn by the memory cell, by comparing the sensed memory cell current against a reference current. If the sensed memory cell current exceeds the reference current, the memory cell is considered an erased cell (e.g., corresponding to a “1” bit). If the sensed memory cell current is below the reference current, the memory cell is considered a programmed cell (e.g., corresponding to a “0” bit).
In practice, it is desirable to have the sensed memory cell current be greater than or less than the reference current by a sufficient margin (referred to herein as the “read margin” in the present application) so as to accurately identify the charge level stored by the memory cell. However, when high density memory devices are implemented with a low supply voltage (“VCC”), such as 1.8 volts, for example, the read margin is significantly reduced. When the read margin is significantly reduced, the reliability of sensing the memory cell current also decreases. The reliability and accuracy of the read operation are thus reduced, resulting in poor performance of the memory device.
Accordingly, there is a strong need in the art to overcome deficiencies of known sensing circuits and to provide a fast and accurate sensing circuit and technique for low voltage semiconductor memory devices.